The invention relates to a DRAM memory.
DRAM semiconductor memories are integrated circuits for storing binary data. In random access semiconductor memories, the memory cells are arranged in matrix form in a memory cell bank. A semiconductor memory chip can contain a plurality of memory cell banks. A RAM (Random Access Memory) is a main memory which allows rapid storage (writing) and reading of data, writing and reading being separate operations. During reading, the stored data information is not erased. During writing, the previously stored information is overwritten. DRAM stores are volatile memories which lose their information when the operating voltage is switched off, which means that storage requires the presence of the supply voltage and a periodic data refresh operation. A memory cell bank comprises a multiplicity of memory cells arranged in matrix form. These memory cells are activated by means of internal row and column access instructions. This memory cell usually comprises integrated MOS capacitances for storing a charge. A selection transistor can be used to connect the capacitance to a bit data line which is connected to an extremely sensitive amplifier (sense amplifier). The gate of the selection transistor is actuated by the selection line.
To access a memory cell, the row or selection line is first of all selected or activated and then the data lines arranged in column form are selected using a column access operation. An external row precharge instruction or autoprecharge (APC) is used to put the memory cell into a state before it is activated. To this end, the selection line or row of the memory cell is decoupled by the sense amplifier. When a read instruction (Read) or a write instruction (Write) is received, an automatic precharge or autoprecharge is normally initiated within the DRAM chip.
To execute an automatic precharge at a predetermined adjustable interval of clock cycles after a read or write access operation to a DRAM store, an autoprecharge counter or APC counter is provided within the DRAM store, said counter counting an adjustable number of clock cycles and, when this number of clock cycles has been reached, outputting an autoprecharge instruction APC which initiates the precharge within the memory cell bank. Autoprecharge counters are programmable for a flexible counting range.
FIG. 1 shows a block diagram of a conventional DRAM store. The DRAM store comprises at least one memory cell bank with a multiplicity of memory cells which can be activated by means of internal row and column access instructions. For each memory cell bank within the DRAM chip, there is an associated APC counter for delaying a column access instruction with autoprecharge (APC).
The DRAM chip receives an external memory access instruction via an external instruction bus, said instruction being decoded by a command decoder provided in the DRAM chip. The command decoder produces row access instructions and column access instructions. The row access instructions comprise, in particular, an activation row access instruction (ROW-act) and a precharge row access instruction (ROW-pre). Column access instructions comprise, in particular, a write column access instruction (WR) with autoprecharge (APC) and a read column access instruction (RD) with autoprecharge (APC). In addition, there is a read column access operation (RD) and a write column access operation (WR) without autoprecharge (APC), the precharge operation being performed automatically; for the purpose of generating the column access instructions and the row access instructions the command decoder requires different decoding times. In this context, the decoding time for generating column access instructions (WR-APC, RD-APC) is shorter than the decoding times TDEC2 for generating row access instructions such as ROW-act, ROW-pre. The column access instructions WR-APC and RD-APC produced by the command decoder are respectively delayed by an associated shift register SR. These shift registers SR are programmable for the purpose of setting latencies. The shift registers SR output the internal column access instructions (WR-APCint, RD-APCint and WR, RD without APC) delayed in accordance with the programmed latency, and these instructions are supplied to the autoprecharge counter. The shift registers SR are clocked by an internal clock signal CLKint in the DRAM chip. The internal clock signal CLKint is produced from an external clock signal CLKext by delaying the external clock signal using a delay circuit with a particular time delay ΔT. The delay circuit is used to compensate for the different decoding times for the row access instructions and the write access instructions. The APC counter, which, in the case of the DRAM chip based on the prior art which is shown in FIG. 1, is likewise clocked by the internal clock signal CLKint, delays the applied internal column access instruction in accordance with an associated start value which is read from a start value memory. When a set final value has been reached, the APC counter outputs an internal autoprecharge instruction APC. An OR gate receives the internal autoprecharge instruction and logic ORs it with the precharge row access instruction which is output by the command decoder in order to actuate an internal memory bank controller which resets a row selection control signal (ROW-SELECT) for selecting a memory cell row to the memory cell bank, i.e. ROW-SELECT is set with ACT and is reset with PRE.
FIGS. 2a, 2b illustrate access to a memory cell within the memory cell bank based on the prior art. In this case, the DRAM store sends a read instruction via the external instruction bus. First of all, as FIG. 2a shows, a row is activated within the memory cell matrix by virtue of the internal memory bank controller, having received an activation row access instruction (ROW-act) from the command decoder, generating a row selection control signal (ROW-sel) following receipt of a rising signal edge of the internal clock signal, the result being a signal delay in ΔtROW. This signal delay ΔtROW is relatively uncritical, since the actual access to the memory cell does not take place until after a subsequent column access operation, as shown in FIG. 2b. When the memory cell row has been selected, as shown in FIG. 2a, the actual data access follows in a column access operation after the shift register SR has output an internal read instruction (RDint). The delay time between the rising edge of the internal clock signal and the application of the internal read instruction should be as short as possible in this case.
The conventional DRAM store shown in FIG. 1 has the drawback that the delay time ΔT for delaying the external clock signal CLK is determined by the longest decoding time in a command decoder. In order to decode the row access instructions ROW-act and ROW-pre, the command decoder requires a much longer decoding time than for decoding the column access instructions WR-APC, RD-APC. The time delay ΔT for generating the internal clock signal CLKint is therefore set in accordance with the longest decoding time, i.e. in accordance with the decoding time for decoding a row access instruction, in the case of the conventional DRAM store shown in FIG. 1. Since the DRAM chip based on the prior art, as is shown in FIG. 1, has only one common internal clock signal or one clock signal domain which, in particular, also clocks the shift registers SR for the column access instructions, the result of the delay in the clock signal CLK in accordance with the longest necessary decoding time DDECmax within the command decoder is that the column access time and hence the memory access time increase.
Although simply splitting the clock domains into two clock domains for pure row access instructions and column access instructions, as is shown in FIG. 3, results in a reduction in the column access time, this may lead to the internal autoprecharge instruction (APC) being generated one clock cycle too late. In the case of the DRAM chip shown in FIG. 3, the chip contains a clock signal delay circuit having two different delay lines, with an internal column clock signal CLKCOLUMN and an internal row clock signal CLKROW being generated. The DRAM chip shown in FIG. 3 is not a DRAM chip based on the prior art, but rather is used merely to illustrate the problem on which the invention is based. The first delay ΔT1 is used to produce the internal column clock signal and is shorter than the second delay ΔT2 for generating the internal row clock signal. The first delay ΔT1 is set in accordance with the first decoding time TDEC1 in the command decoder for the purpose of producing the column access instruction. The second delay time ΔT for generating the internal row clock signal is set in accordance with the second decoding time TDEC2 in the command decoder for the purpose of generating a row access instruction. Although splitting the clock domains into two clock domains reduces the column access time, it results in a signal transition between two clock signal domains, namely at the location between the outputs of the shift register SR and the inputs of the autoprecharge counter. The internal column access instruction which is respectively output by the shift registers SR initiates the APC counter, but this is clocked by the column clock signal CLKint-ROW, i.e. in the other clock signal domain. This can result in the APC counter counting one clock cycle too many, which means that the internal precharge instruction APC is output one clock cycle too late. In this case, the ROW precharge time TRP, i.e. the period between precharge and activate, prescribed by the specification is infringed.